1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device comprising a protective circuit for protecting a semiconductor chip from externally intruding static electricity.
2. Description of the Related Art
FIG. 18 shows a wafer 65 during manufacture of a semiconductor chip and a plurality of semiconductor chips 66 provided on the wafer 65. A peripheral region of the semiconductor chip 66 is a so-called scribe region 3 which is used to separate the semiconductor chips 66 on the wafer 65. After the wafer is separated into the individual semiconductor chips 66, the scribe region 3 is cut away by dicing. At the four sides along the scribe region 3 of the semiconductor chip 66, a plurality of signal input cells, signal output cells, or signal input/output cells 2 for giving and receiving a signal to and from the outside are provided (hereinafter, input cells, output cells, or input/output cells are collectively referred to as “I/O cells”). Each I/O cell 2 has an electrode pad (not shown in FIG. 18), and gives and receives a signal to and from an external circuit via the electrode pad.
In recent years, as the number of signals is increased in order to extend functions, the number of required electrode pads is also increased. Therefore, the size of the semiconductor chip 66 is often determined by the number of electrode pads.
To reduce the size of the semiconductor chip 66, for example, Japanese Unexamined Patent Application Publication No. 2000-164620 discloses an arrangement in which, as shown in FIG. 19, each I/O cell 2 is caused to have a small cell width W and the electrode pads 1 for external connection of the I/O cells 2 are vertically provided in a zigzag pattern between the scribe region 3 and the I/O cell 2. Note that, in FIG. 19, 30 indicates wirings for connecting the electrode pads 1 and the I/O cells 2.
Conventionally, further, to reduce the size of the semiconductor chip 66, for example, Japanese Unexamined Patent Application Publication No. 2004-296998 discloses that, as shown in FIG. 20, an electrode pad 1 for external connection is provided above an I/O cell 2 so that the area of a space between an I/O cell 2 and a scribe region 3 is reduced.
In a semiconductor chip, a protective circuit for protecting the semiconductor chip from externally intruding static electricity is provided in each I/O cell 2. In the semiconductor chip having the protective circuit, as shown in FIG. 21, static electricity intruding from the outside of the semiconductor chip is caused to escape from the electrode pad 1 for external connection via a ground-side protective circuit 6 in the corresponding I/O cell 2 to a ground wiring 5, or from the electrode pad 1 via a power source-side protective circuit 7 in the corresponding I/O cell 2 to a power source wiring 4. The potential of the ground wiring 5 is often caused to be the same as the potential of the substrate of the semiconductor chip 66.
The present inventors found that, in the I/O cell 2 having the protective circuits 6 and 7, resistance against static electricity can be enhanced basically by reducing a distance between the electrode pad 1 and the ground-side protective circuit 6 of the corresponding I/O cell 2 to lower a resistance value therebetween. Therefore, in the arrangement disclosed in Japanese Unexamined Patent Application Publication No. 2004-296998, the distance between the electrode pad 1 and the ground-side protective circuit 6 of the corresponding I/O cell 2 is short, and the distance does not vary much among the I/O cells 2, so that the resistance against static electricity of each I/O cell 2 is enhanced.
However, it was found that, in the conventional semiconductor integrated circuit devices of FIGS. 20 and 21, although a portion of the electrode pad 1 for external connection closer to the scribe region 3 is positioned above the I/O cell 2, a useless empty space C is present below a portion thereof closer to the scribe region 3, and as a result, the reduction of the size of the semiconductor chip 66 is hindered. Specifically, since circuits, such as an internal logic circuit and the like, other than the I/O cells 2 of the semiconductor chip 66 are present in inner portions of the semiconductor chip (closer to the center of the chip, i.e., a side opposite to the scribe region 3 of the I/O cell 2), the empty space C present between the scribe region 3 and the I/O cell 2 is difficult to use and is useless.